The present invention relates to a non-volatile memory device, more particular to a common source line control scheme of a non-volatile memory device capable of improving a read characteristic.
There is increasing demand for semiconductor memories that can be electrically erased and programmed without refreshing data stored in the memories themselves. Also, there is a trend toward enhancing the storage capacity and the density of integration in memory devices. A NAND-type flash memory is one example of non-volatile semiconductor memories that provide high capacity and integration density needless of refreshing data stored therein. The flash memory devices retain their stored data even when their power supplies are interrupted. Thus, non-volatile memory devices are widely used in electronic devices such as portable terminals, portable computers, and the like, which are usually situated in an environment in which the possibility of power supply interruption is present.
Non-volatile memory devices such as NAND-type flash memory devices include electrically erasable and programmable read-only memory cells as their own memory cells. In general, a memory cell includes a cell transistor. The cell transistor includes a semiconductor substrate (bulk) of first conductivity (e.g., P-type), spaced source and drain regions of second conductivity (e.g., N-type) in the substrate, a channel region at a face of the substrate, between the spaced source and drain regions, a floating gate for storing charge carriers when the device is programmed, and a control gate which overlies the floating gate.
FIG. 1 shows a memory cell array 10 with memory cells having the construction mentioned above. Referring to FIG. 1, the memory cell array 10 includes a plurality of cell strings 11 (or called NAND cell strings). Each of the cell strings 11 is composed of a string selection transistor SST as a first selection transistor, a ground selection transistor GST as a second selection transistor, and a plurality of memory cells MC0˜MCm serially connected between the string selection transistor SST and the ground selection transistor GST. The string selection transistor SST includes a drain connected to a corresponding bit line (BL0 to BLn) and a control gate connected to a string selection line SSL. The ground selection transistor GST includes a source connected to the common source line CSL and a gate connected to a ground selection line GSL. Furthermore, between a source of the string selection transistor SST and a drain of the ground selection transistor GST, the memory cells MCm˜MC0 are serially connected with each other. The memory cells MCm˜MC0 are respectively connected with corresponding word lines WLm˜WL0.
As shown in FIG. 1, bit lines BL0˜BLn are connected to page buffers PB0˜PBn, respectively. As will be known by those skilled in the art, each page buffer functions as a sense amplifier during a read operation and a write driver during a write operation. Examples of the page buffers are disclosed U.S. Pat. No. 5,936,890, entitled “SEMICONDUCTOR FLASH MEMORY HAVING PAGE BUFFER FOR VERIFYING PROGRAMMED MEMORY CELLS”, and U.S. Pat. No. 6,671,204, entitled “NON-VOLATILE MEMORY DEVICE WITH PAGE BUFFER HAVING DUAL REGISTERS AND METHODS OF USING THE SAME”, incorporated by reference herein.
The common source line CSL is connected with the common source line driving circuit 20. The common source line driving circuit 20 of FIG. 1 corresponds to a part of an erase voltage adjusting means 10 shown in FIG. 3 of U.S. Pat. No. 5,696,717. The common source line driving circuit 20 includes a depletion MOS transistor 21 and an NMOS transistor 22. Channels of the depletion MOS transistor 21 and the NMOS transistor 22 are serially connected with each other between the common source line CSL and a reference voltage having a ground voltage. A power supply voltage VDD is applied to a gate of the depletion MOS transistor 21, and a control signal READ is applied to a gate of the NMOS transistor 22. The control signal READ is activated at a high level during the read operation, whereas it is inactivated at a low level during residual operations. The read operation includes program/erase verification read operations as well as a read operation. When a high voltage is transferred to the common source line CSL, the depletion MOS transistor 21 prevents the NMOS transistor 22 from being broken.
Although a memory cell array 10 having only one memory block is shown in FIG. 1, it will be apparent to those skilled in the art that the memory cell array has more memory blocks. Accordingly, the common source line CSL is arranged at the memory cell array 10 to be shared by the memory blocks.
As will be understood by those skilled in the art, the read operation is divided into a precharge interval, a develop interval, and a sense interval. During the precharge interval, bit lines BL0˜BLn are charged with a predetermined precharge voltage by corresponding page buffers PB0˜PBn. During the develop interval, electric potentials of bit lines become lower or are maintained according to states of selected memory cells. For example, when a selected memory cell is an on-cell or an erased memory cell, a sense current supplied from a page buffer flows in the common source line CSL through a cell string having a selected memory cell. This causes the electric potential of the bit line to be lowered. In contrast to this, when the selected memory cell is an off-cell or a programmed memory cell, the sense current supplied from the page buffer is interrupted by the selected memory cell, namely, the programmed memory cell. This causes the electric potential of the bit line to be maintained. During the sense interval, a corresponding page buffer senses the electric potential of each bit line. During the read operation, as shown in FIG. 2, the control signal READ is activated at a high level. This level causes a current flowing in the common source line CSL through cell strings to be discharged by the common source line driving circuit 20.
During the read operation, as shown in FIG. 2, the control signal READ is activated at a high level, thereby discharging a current of the common source line CSL through the NMOS transistor 22. As known by those skilled in the art, a current driving performance of a depletion MOS transistor 21 is lower than that of an NMOS transistor 22 under the same condition. For this reason, in the case of the common source line driving circuit 20 shown in FIG. 1, a current discharge of the common source line CSL is not restricted by the NMOS transistor 22, but is restricted by the depletion MOS transistor 21, the gate of which is coupled to a power supply voltage VDD. During the develop interval, when increased current flows in the common source line CSL, as shown in FIG. 2, the common source line CSL is not maintained at a ground voltage. This results from an RC loading of the common source line CSL that is coupled to an entire part of the memory cell array.
When a current flowing in the common source line CSL is not sufficiently discharged during a develop interval of the read operation, it is difficult to discriminate a state of the selected memory cell. This means that it takes a long time to sense program/erase states of the selected memory cell. Furthermore, in the worst case, the on-cell can be sensed as an off-cell, causing the deterioration of a read characteristic.